Welcome to HT-Lab

On this site you will find several FPGA/ASIC IP cores, some EDA Utilities and HowTo documents. Most of the IP Cores are written in generic VHDL and supplied in full source.

If you have any questions or comments please use the feedback form. For commercial inquiries you can contact HT-Lab via sales at ht-lab dot com.

If you are looking for the CPU86 8086 IP Core then click here (updated 25/07/14).

Need to convert VHDL to SystemC? try the alpha release of vh2sc.exe.

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Interested in SystemC Synthesis?  then check out SystemCrafters.

Looking for some high-quality prototype boards, need some custom boards? Navigate to Enterpoint FPGA and Asic Design.

Do you know VHDL? then try to answer this question, .............. the correct answer is here. If you are learning VHDL then this VHDL handbook might be useful. VHDL2008 has been approved by Accellera, Jim Lewis has an excellent presentation on some of the language enhancements.

constrTurtle2.gif If you are interested or involved in FPGA designs for fault tolerant systems, avionics, space or reconfigurable hardware then the yearly MAPLD conference is the place to be. Details of this excellent conference can be found at KLABS.

 Focus is a product from FishTail Design Automation which automatically detect false and multi-cycle path in your design. The output is a set of SDC constraints which can be used for Synthesis, P&R and STA, see EEDESIGN article here.

If you are serious about programming in TCL/TK I would definitely recommend attending the excellent TCL/TK Doulos courses. You will not only learn how to program in TCL/TK but also learn how to use it with Modelsim.

 Solidify is a Static Verification (property checker) tool from Averant Inc.  Using Solidify the user can fully validate his design using Averant's HPL language, SVA or PSL. Solidify also contains an automatic property generation option which can be used to validate multi-cycle path constraints, check for unreachable states and deadlock in FSMs, deadcode, array boundary violations, tri-state violations and more.

While we are on the subject of assertions, this is how you should use assertions/report command (thanks to BlueARC in the UK :-)

After you have generated all those timing exception with Focus you can use Solidify, Magallen, 0-In or SolidTC to validate them. The advantage of SolidTC is that it checks the SDC file directly.

Looking for a JTAG on-chip FPGA/ASIC debugger on steroids? would like to create a hardware testbench?, want to translate SVA/PSL into a hardware monitors? then try Temento's DiaLite!

What's new.....

25-Jun-14 : Minor updates to CPU86, some package options were missing, added GHDL script
10-Mar-13 : General update.

09-May-10 : Added HTLSPIm Master SPI controller IP Core.

08-Nov-09 : Added HTL16550 UART Commercial IP Core.

08-Aug-09 : Uploaded ISS186 Instruction Set Simulator ver 0.1.

02-Aug-09 : Uploaded CPU86 ver 0.81, fixed call [reg] bug.

07-Dec-08 : Added Modelsim Remote Control demo using Tcl.

17-May-08 : Uploaded CPU86 ver 0.75, several bug fixes.

18-Aug-07 : Uploaded SystemC for VHDL engineers tutorial.

14-Oct-07 : Added HTL8255 Commercial IP Core.

19-Aug-07 : Uploaded first part of SystemC for VHDL engineers tutorial.

07-Jul-07 : Added simple page on how to install SystemC 2.2 under Cygwin.

13-May-07 : Added VMWare Player Gentoo on Win2K Howto page.

10-Mar-07 : Added VHDL to SystemC converter.
07-Jan-07 : Added Mersenne Twister MT32 design.
29-Oct-06 : Created a simple wrapper for the Opencores 16550 UART and combined all cores into a single file.
07-Oct-06 : CPU86 ver 0.69, fixed INTR Logic and SHL instruction(thanks to Rick Kilgore)
23-Sep-06 : CPU86 ver 0.68, fixed INTA vector read logic (thanks to Rick Kilgore)
01-May-06 : Added simple Morse Generator in VHDL
31-Jan-06 : VHDLSort Updated to Version 0.85
29-Jan-06 : Added CoLinux Windows Howto page
08-Jan-06 : Serial Divider overflow detection bug fixed (thanks to F. Munchow-Pohl)
22-Dec-05 : VHDL Source files for CPU86 now available
03-Sep-05 : Ported CPU86 to ProASIC+ Board
27-Aug-05 : Updated CPU86 page with some EDIF cores for FPGA implemenation
25-Aug-05 : MON88, 8088/8086 Debug Monitor added
19-Jun-05 : Updated CPU86 model (changed to 8088)
22-May-05 : Free 128bits AES IP core added
13-Mar-05 : Updated VHDLSORT and GUI
05-Mar-05 : Renamed site to Home Tech since it is definitely not High-Tech :-)
30-Jan-05 : Simple Binary to Intel Hex converter added
02-Oct-04 : VHDL Dependency Sort updated to version 0.6
02-Oct-04 : Added the CPU86 Free 8086 Modelsim Simulation model page
28-Sep-04 : Updated Mentor-Linux install page for Gentoo Linux
11-Jul-04 : Displaying Remote X clients using Cygwin added
25-Jan-04 : Beta AutoCheck Builder utility added
31-Dec-03 : Date2HDL TCL utility page added

30-Nov-03 : New version of VHDLDS (0.3) uploaded
16-Nov-03 : Nios Chess engine port added to the free core section
11-Oct-03 : TV Ping-Pong game added to the free core section
05-Oct-03 : Modelsim/Precision version numbers updated
13-Sep-03 : UART2FLI Interface example added
06-Jul-03 : VHDL Dependency Sort Utility added
29-Mar-03 : Fix point Cordic module added
23-Mar-03 : Serial/Parallel Multipliers/Dividers added
21-Mar-03 :
Link to UK Modelsim User Conference presentations added
09-Mar-03 : Published papers page updated
08-Mar-03 : Replaced MOVE Processor files (not sure about the version)
02-Mar-03 :
The MOVE and LEON zip files are corrupted! do not use!
20-Feb-03 :
Added Modelsim Socket/FLI demo (Fractal Fern Generator)
16-Feb-03 :
Started to evaluate Namo Webeditor(now ordered)
23-Nov-02 :
Rcore54 Risc Processor Added
20-Aug-02 :
Added Linux Modelsim/HDS/Precision Install guide
20-Aug-02 :
MAPLD2003 Conference details added
14-Aug-01 :
MAPLD and DASIA papers added
14-Aug-01 : MAPLD2002 Conference details added
13-Jun-01 :
MAPLD2001 Conference details added


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