PC Compatible Real Time Clock
The HTL146818 is a synchronous implementation of the industry standard 146818 Real Time Clock (RTC). The RTC provides a real-time clock, calendar and alarm function. In addition, 50 bytes of user memory, a programmable periodic interrupt and a square wave function are also provided.
The RTC provides a real-time clock function in either 24 or 12-hour format with AM/PM indication. A time alarm can be programmed to trigger from once a second up to once a day. The calendar function compensates for leap-years up to the year 2099. The time, alarm and calendar values can be programmed in either binary or BCD format. Three maskable interrupts (IRQ output) are provided to inform the processor of a Alarm trigger, End of Update trigger and a general
purpose Periodic trigger. The End of Update trigger is provided so that registers can be updated without conflicting with the internal update function. The Periodic interrupt can be programmed to trigger from 30.5us up to 500ms. The square wave output pin (SQW) can output one of the 13 taps from the internal 22 bits divider creating a 50% duty cycle signal which can range from 8.192KHz down to 2Hz. The RTC is clocked from a 32.768KHz oscillator (OSC1) which is internally synchronised to the main
processor clock.
Key Features
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Functional compatible with the 146818 RTC
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Fully Synchronous with generic processor/controller interface
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Counts seconds/minutes/hours/days/day of the month/day of the week/years
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Compensates for leap-years up to 2099
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Binary of BCD Time representation
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12 or 24 Hour clock with AM/PM indicator
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Time of Day alarm from once a second up to once a day
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Square Wave output with frequencies from 8.192KHz down to 2Hz
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End of Update Interrupt.
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Periodic Interrupt from 30.5us up to 500ms
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Three maskable interrupts
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50 user Bytes.
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Clocked from a 32.768KHz oscillator
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Written in technology independent VHDL
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Asynchronous reset
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Lowest cost commercial 146818 compatible core
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Area and Performance
The table below shows a push button implementation of the standalone core for the 3 major FPGA vendors. The values given are only a rough indication of the required area and performance. Mentor Graphic's Precision RTL 2007a.8 was used for synthesis.
| Vendor |
FPGA Type |
Area |
Fmax (note1) |
P&R |
| Actel |
ProASIC3 A3P125-2 |
2022 Tiles (65%) |
110MHz (130MHz) |
Designer 8.1 |
| |
Iglo AGL125V2 |
1897 Tiles (62%) |
83MHz (100MHz) |
|
| Altera |
CycloneIII EP3C5 |
931 LE (18%) |
240MHz (250MHz) |
Quartus 7.2 |
| |
StratixIII EP3SE50-2 |
575 CAluts (2%), 521 Regs(1%) |
271MHz (275MHz |
|
| Xilinx |
Spartan3E 3s100 |
261 Slices (27%) |
184MHz (200MHz) |
ISE 9.2i |
| |
Virtex5 5VLX30 |
136 SlicesR (1%), 263 SliceL (1%) |
379MHz (380MHz) |
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Note1: Clock 'clk' constraint
Programming Model
It is recommended to download one of the many commercial 146818 datasheets to understand the programming model. The HTL146818 contains a number of differences between these devices:
- The HTL146818 only provides a single 32.768KHz time basis. It is trivial to add other (multiple) frequencies.
- There is no restriction in changing the Data Mode (DM) bit, i.e. the driver can change this bit without re-initialising the registers. However, the DM bit must be set to the correct value during a write cycle to the Time, Date and Alarm registers (address 0x00 to 0x09).
- The HTL146818 logic is clocked from the clk input pin and not from the OSC1 input. The OSC1 clock edges are only used as an enable for the update logic. This means generally that the update time is significantly faster than the original 146818 device. The worst case update time is 6 clk cycles.
- Register D is added for compatibility reasons, the VRT bit is not used and will always read back as '1'.
- The Daylight Saving Mode is not implemented hence the DSE bit in Register B is ignored.
- The first update after writing "010" to DV2:0 occurs 500msec later.
Deliverables
The HTL146818 is delivered in synthesisable vendor independent VHDL source code. The source code is fully documented and can be synthesized using any modern synthesis tool. A self-checking VHDL testbench is included which verifies the different functions. Software driver examples are provided in C and assembly (x86 processor family only).
For evaluation the HTL146818 can be supplied on a low-cost FPGA development board from Enterpoint Ltd. The HTL146818 is instantiated together with the CPU86 8088 processor, an 8259 Interrupt controller, an 8255 Parallel Interface unit (to drive an optional HD44780 LCD interface), a UART and 40Kbyte of SSRAM. No VHDL source files will be supplied in this case.
HTL146818 Evaluation on the Enterpoint Drigmorn1 FPGA prototype board
Price
Single Project............................ £-- (All prices in UK Pounds)
Unlimited Project....................... £--
Evaluation (Drigmorn1+bitfile)... £TBC
Contact HT-Lab for further information.
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