Universal Asynchronous Receiver/Transmitter with Configurable FIFO's

The HTL16550 is an industry standard functional compatible 16450/550 Universal Asychronous Receiver Transmitter (UART).  Individual configurable FIFO depth for the transmitter and receiver can be set up to reduce the number of CPU interrupts. The UART includes a programmable baudrate generator capable of dividing the system clock by 2 up to 65535. The baudrate output signal has a 50% duty cycle for even values and a [(clk/2)+1 high, clk/2 low] for odd values. For System On Chip applications the baudrate output signal can be configure to a clock pulse period reducing resource requirements.

Using a USB_to_TTL converter cable communications speeds in access of 1Mbps can be achieved.



 

Key Features

  • Functional compatible with the industry standard 16450/550

  • Configurable FIFO depth

  • Readable FIFO fill levels

  • DMA support signals

  • Programmable Interrupt Generation

  • Fully Programmable Serial functions:

    • 6,7 or 8-bit characters

    • Even, Odd, None, Sticky Parity

    • 1,2 stop bits Generation

    • Baudrate Generation up to clock period.

    • False Start bit detection

    • Line Break Generation and Detection

    • Full Loopback Diagnostic.

    • Modem Control functions

  • Independent Receiver Clock input

  • Simple uProcessor/uController Interface

  • No internal tri-state busses

  • Fully synchronous

  • Written in technology independent VHDL

  • Lowest cost commercial 16550 IP core 

 

Area and Performance

The table below shows a push button implementation of the standalone core for the 3 major FPGA vendors. The values given are a rough indication of the required area against performance. No pin number, slewrate or I/O type was specified, only a clock constraint of 100MHz was given. Mentor Graphic's Precision RTL 2009 was used for synthesis.

Vendor FPGA Type Area Fmax P&R
Actel ProASIC3 A3P060-2 VQFTP100 782 Comb, 299 Seq 93.0MHz Designer 8.6
Altera CycloneIII EP3C5E 144C-7 555 LE (270 FF, 304 memory bits) 97.8MHz Quartus 9
Xilinx Spartan3E 3S100 CP132-4 373 Slices 102.3MHz ISE 11.3


Deliverables

The HTL16550 is delivered in synthesizable vendor neutral VHDL source. The source code is fully documented and can be synthesized using any modern synthesis tool. A partial self-checking VHDL testbench is included which verifies the different serial modes.

For evaluation the HTL16550 can be supplied on a low-cost FPGA development board from Enterpoint Ltd. The HTL16550 is instantiated together with the HTL80186 processor, an HTL8259 Interrupt controller, an HTL8254 Programmable Timer,  a 146818 compatible Real Time Clock, an HTL8255 Parallel Port Interface, a Watchdog timer and 40Kbyte of embedded SRAM. No VHDL source files will be supplied in this case.


HTL16550 Evaluation on the Enterpoint Drigmorn1 FPGA prototype board

Pricing

HTL16550 VHDL Source...............  *** Contact HT-Lab ***
Drigmorn1 Evaluation Board......... *** Contact Enterpoint ***
Avit Research USB_2_TTL Cable.... *** Contact Avit Research ***
USB_2_RS232 Cable.................... *** See Ebay/Web ****

Preferred payment is via PayPal but other methods are available upon request. 

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