80186 Compatible FPGA/ASIC IP Core
The HTL80186 is a high-performance embedded processor core supporting an instruction set identical to an Intel's© 80186 microprocessor. The HTL80186 is software compatible with the 8088, 8086, 80188 and 80186 microprocessors from Intel/AMD and uses standard 16bits compilers and development tools. The processor can be configured for an 8bits (80188) or 16bits (80186) external databus and/or behave like an 8088/86 processor. The extended addressing mode first introduced by VAutomation's Turbo186 cores is also supported. Enabling this mode extends the real mode addressing range from 1MByte to 16Mbyte. The Turbo186 mode is supported by Paradigm C++ IDE and Micro Digital's SMX real time kernel.
Note: the HTL80186 is a microprocessor core without any embedded peripherals, however these can easily be added and are available from HT-Lab and other IP vendors. For a 186 based microcontroller see the HTL186C core.
A non-cycle accurate Instruction Set Simulator is available as a free download from here.
Key Features
- Instruction Set Compatible with the industry standard 80186/80188 Processor
- Can be configured for 8 or 16 bits external databus
- Can be configured to behave like an 8086/8088
- Supports the Turbo186 Extended addressing mode
- A20 Address line support
- Written in vendor neutral VHDL
- Can fit in a low-cost small FPGA like a Spartan S500 (49% used)
- Full RTL source code and EDIF netlist available
- Lowest cost commercial 80186 CPU core available
Differences with the original 80186
- The HTL80186 is a CPU core only, no peripherals are supplied as standard.
- The HTL80186 is not cycle accurate, instruction might take less or more clock cycles to complete.
- The HTL80186 is bus cycle, but not bus timing accurate.
- The HTL80186 has not been validated with an 80187 Coprocessor or in a multi-processor configuration.
- The HTL80186 supports the A20 address line, this is used by some DOS memory managers to address more than 1MByte.
- The HTL80186 utilises a 7 bytes prefetch queue in both the 8 and 16 bits modes
Deliverables
The HTL80186 can be delivered in a padless EDIF netlist version for Xilinx, Altera or Actel or in full vendor neutral synthesizable VHDL source. The source code is fully documented and can be synthesized using any modern synthesis tool. Synthesis examples are provided for Xilinx XST and Altera QNS.
A simple testbench is provided which boots FreeDOS from a bank switched memory image.
For evaluation the HTL80186 can be supplied on a low-cost FPGA development board from Enterpoint Ltd. The HTL80186 is instantiated together with a number of perhipherals such as the HTL8254 Programmable Timer, HTL8259 Programmable Interrupt Controller, HTL16550 UART, HTL8255
Parallel I/O, HTL146818 RTC, Watchdog timer and 40Kbyte of SSRAM. No VHDL source files will be supplied in this case.
Other prototype boards such as Enterpoint Drigmorn2, Digilent Nexys2 and Actel's Cortex M1 boards are also supported. A porting service to other FPGA boards is also available.
Figure: HTL80186 Evaluation Board
Pricing
HTL80186 EDIF netlist (no source).... *** Contact HT-Lab for the latest price ***
HTL80186 Full VHDL Source.............. *** Contact HT-Lab for the latest price ***
Drigmorn1 Evaluation Board.............. *** Contact Enterpoint ***
Preferred payment is via PayPal but other methods are available upon request.
Contact HT-Lab for further information.
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