Programmable Interrupt Controller IP-Core

The HTL8259 is a synchronous implementation of the industry standard 8259/8259A Programmable Interrupt Controller (PIC). The PIC can be used to extend the number of interrupt lines on a microcontroller/processor. Although the PIC is normally used in an x86 design, the VHDL source code can easily be modified to adopt to a non-x86 style microcontroller/processors.

The HTL8259 provide a wide range of vectored interrupt handling and ternination modes. The controller can be programmed for fixed, priority and polled mode of operation. Interrupt inputs can either be level or edge triggered. A single HTL8259 controller can handle up to 8 vectored priority interrupts. Without any glue logic multiple HTL8259 can be cascaded to provide upto 64 vectored priority interrupts. This number can further be increased by using the Poll command.

The HTL8259 is delivered in vendor neutral VHDL and can be synthezised for a wide range of FPGA/ASIC's.

 

Key Features

  • Functional compatible with the industry standard PIC 8259

  • Fully synchronous

  • End Of Interrupt modes

    • Automatic

    • Automatic with Rotation

    • Specific

    • Specific with Rotation

    • Non-Specific

  • Fully and Special Fully nested mode

  • Special Mask mode

  • Buffered Mode

  • Cascade mode with Master/Slave selection

  • Edge and Level triggered interrupt inputs

  • No internal tri-state busses

  • Fully synthesisable

  • Written in technology independent VHDL

  • Asynchronous reset

  • Lowest cost commercial 8259 core

 

Area and Performance

The table below shows a push button implementation of the standalone core for the 2 major FPGA vendors. The values given are an indication of the required area and performance. No pin number, slewrate, I/O type etc was specified. Xilinx ISE and Altera Quartus were used for synthesis and Place&Route.

Vendor FPGA Type Area Fmax P&R
Altera CycloneII EP2C5 F256C 418 LE 120.7MHz Quartus 9
Xilinx Spartan3 x3s50 248 Slices 71MHz ISE 11.1


Differences with the original VLSI 8259

There are a number of differences between the original 28 pins VLSI device from Intel and others and the HTL8259,

Deliverables

The HTL8259 is delivered in synthesizable vendor neutral VHDL source code. The source code is fully documented and can be synthesized using any modern synthesis tool. A self-checking VHDL testbench is included which partly verifies the different operating modes.

For evaluation the HTL8259 can be supplied on a low-cost FPGA development board from Enterpoint Ltd. The HTL8259 is instantiated in dual cascade mode together with an HTL80186 processor, the HTL16550 UART,  a Real Time Clock, the HTL8254 Timer unit and 40Kbyte of SSRAM. No VHDL source files will be supplied in this case, just a bitstream.

The following interrupt sources are available for testing:

Master 8259 Interrupt Source
IRQ0 8254 Timer0, PC Timer Tick
IRQ1,6 External I/O Pin
IRQ3 UART (COM1)
IRQ4 UART (COM2)
IRQ5,7 8255
Slave 8259  
IRQ8 Real Time Clock
IRQ9..14 External I/O Pin
IRQ15 Watchdog Timer

 


HTL8259 Evaluation on the Enterpoint Drigmorn1 FPGA prototype board

Pricing

HTL8259 VHDL Source...............        *** Contact HT-Lab ***
Drigmorn1 Evaluation Board....... £50 *** Contact Enterpoint for latest prices ***

Preferred payment is via PayPal but other methods are available upon request. 

Solution Graphics

 

 

 

Contact HT-Lab for further information.

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