Miscellaneous VHDL Cores
- Double Bit Correcting Memory EDAC (17KB zipped)
See published DASIA 2000 Paper for more info
- Generic Signed/Unsigned Multipliers
Serial Signed/Unsigned Multiplier
+ Testbench (4KB zipped)
Parallel
Signed/Unsigned Radix-4 Multiplier + Testbench (4KB zipped)
Note:
for RTL designs it is advisable to use the '*' operator which will result
in an optimised target FPGA multiplier. As far as I know no synthesis tool
will infer a optimised multiplier from the Parallel Radix-4 design.
- Generic Signed/Unsigned Dividers
Serial Signed/Unsigned Divider
+ Testbench (5KB zipped)
Version
0.2 - Overflow Detection bug Fixed by Frank Munchow-Pohl
Parallel
Signed/Unsiged Divider + Testbench (3KB zipped)
