MOVE PROCESSOR

Simple processor based on the TTA concept

Last Updated: 04-Sept-2004

 

This page describes the uTTA (MOVE) processor design. This processor is based on the Transport Triggered Architecture (TTA) which is actively being researched at Delft University in the Netherlands. In contrast to traditional RISC architecture in the MOVE architecture the data movement or destination address initiates the required operation rather than the processor opcode. Before reading on you should check out the sheer wealth of papers and excellent documentation on the subject which you can download from the MOVE Project Home Page

Introduction

I became interested in this architecture after reading a paper by Henk Corporaal, who is one of the leading expert on this architecture and currently the author of the only (?) MOVE processor book published. The MOVE architecture is very simple to implement yet can lead to very powerful parallel architectures. I developed the uTTA processor a few years ago to get a better understanding of this concept. The processor is developed in VHDL using Modelsim 5.4 and synthesised using Synplify 6.0. I wrote a basic DOS based assembler using Borland's C/C++ Builder 5.5, for any semi-serious work you obviously need a high level compiler. Unfortunately due to my workload I never got around modifying or creating one.

Example

 

Figure Simple TTA Processor with 2 Functional Units

To illustrate the TTA architecture the figure above shows a simple TTA processor with 2 Functional Units (FU). These functional units perform operations on the data when certain registers are being addresses. A typical functional unit contains three registers namely, an Operant registers, a Trigger register and a Result register. The trigger register initiates the operation when addressed. For example, a simple addition like Ram20+Ram21=Ram22 is executed as follows,

Oadd <=Ram20 ; Move=0020, Move R1 contents into Operant Register
Tadd <=Ram21 ; Move=0121, Move T2 contents into the Trigger Register
             ; The Adder now performs the operation
Ram23 <=Radd ; Move=2302, Write the result to R3

As can be seen from the above example there is only one instruction (<=) the "move". There are several advantages to the TTA Architecture,

Simplicity
Each unit performs a basic set of instruction, this results in a clear structural processor design.

Flexibility
New operations can easily be implemented by adding extra Functional Units at different address locations. The architecture of each FU can vary (e.g. pipelined and non-pipelined) without affecting the overall complexity.

Performance
Performance can be increased by adding extra FU, pipelining FU, or increasing the transport network (interconnecting FU). Adding extra FU does not required the transport network to be increased, as is the case in VLIW architectures.

Super Scalar
Implementing Super Scalar architecture is simplified due to the parallel connection of the functional units. Multiple instructions can be issues by adding extra data busses. A bus controller is required to prevent multiple data trying to use the same FU and to solve data dependency issues.

Disadvantage of the MOVE (and VLIW) processors are the increased complexity of the compiler and scheduler.

Download source files

The described uTTA architecture is based on the Harvard architecture and requires 16 bits instructions and 8 bits data. Only a basic set of instructions is currently implemented. No internal registers, apart from the FU registers, are available. The uTTA processor is written in VHDL93 and can be synthesised using any modern synthesis tool.

• uTTA VHDL sources and assembler (zip, 85KB)

  If you are using Modelsim you can compile and simulate the design by executing the compile.bat and run.bat batch files. The assembler and some simple testfiles are located in the assembler directory. To run the assembler simply type ASM <source_files.mov>, this will assemble the file and write a VHDL ROM file (furom.vhd) to the src directory.

  For synthesis you need to set a multicycle path on the divider, SDC example:

  set_multicycle_path 4 -to { I8/reg_rquot(*) } -design rtl
  set_multicycle_path 4 -to { I8/reg_ovl/in } -design rtl
  set_multicycle_path 4 -to { I8/reg_rrem(*)/in } -design rtl

Other MOVE links

• Douglas W. Jones High Performance Architecture Course notes describes a MOVE processor
• uTTA Book by Henk Coporaal which you can order from Barnes and Noble