TV Pong Game

Ping-Pong game on an Actel APA075 ProASIC plus

Last Updated: 14-Oct-2003

TV Ping Pong was the first TV game I played as a kid (yes I know that shows you my age:-). I can still remember the light brown/black looking plastic box with 2 gamepads (potentiometers). After connecting it to our B&W TV I saw this amazing ball bouncing on the screen. I never realised I would be writing my own version in VHDL nearly 30 years later. The game itself has very little entertainment value but I guess the entertainment is writing the game itself.  For a full history description and some great hardware shots have a look at this page.

Download VHDL Source Files

Click on the link below to download the VHDL and Actel source files. You can easily port this game to another FPGA/prototype board. For this you need to replace the PLL (PLL.VHD) or use an external 25.176MHz clock. The clock doesn't have to be so accurate since most (multi-sync) monitors can sync-up to a wide range of input frequencies. The zip file contains the pingpong.stp Staple bitstream file so if you have access to an Actel ProASICplus Starterkit you can just upload the file.

The source files are located in the pingpong_lib\HDL directory. You can find a Precision synthesis script and a separate add_file.tcl script in the pingpong_lib\ps\pingpong_struct\hds directory. If you have access to HDL designer than load the pingpong.hdp file in a text editor and correct all the pathnames before invoking HDL_Designer. You can also do this from within HDL_Designer but I find a global find and replace in a text editor quicker to use.

Software/Hardware used

 

Running the Game

The game is very simple, just make sure the ball doesn't hit the wall behind you, if it does then your opponent gets an extra point. The scoring stops when one of the players (the winner) reaches 9. You can clear the score by pressing reset (PB1). The ball and racket speed are controlled by 3 jumpers. All the screen, ball and racket dimensions are defined in a single package and can easily be modified for other platforms.

Simulation

There is no testbench to speak off. I simply checked the waveform in Modelsim to see if the ball/racket coordinates were updated correctly. I was planning to use the FLI interface to drive a graphics display program running under Cygwin (see my Fractal Demo) but I lost interest after the design started to work :-).

Synthesis

For synthesis I used Precision 2003b. The synthesis process only takes a few seconds and the required 26MHz clock constraint is easily met (Designer report 50MHz). After synthesising the design import the pingpong.edf (edif) and pingpong.gcf (pin layout) file into Designer V5 and generated the bit/staple file. You need the gcf file because Designer V5 can not yet handle Precision's SDC file (Synopsys Design Constraint file).

Importer Summary Designer
===============
Part: APA075
        Core Slots:        3072
        RAM/FIFO Slots:    12
        I/O Slots:         158    (Globals: 4)   (PLLs: 2)

Core Cells:                996  -->  Usage: 32.4 percent
RAM/FIFO Cells:            0    -->  Usage: 0.0  percent
IOs:                       17   -->  Usage: 10.9 percent
PLLs:                      1    -->  Usage: 50.0 percent

Hardware Description
 

If you don't have access to HDL_Designer 2003 you can click here to browse the design (requires Java script support). The game consist of 6 modules as shown in the HDL_Designer screenshot above. The functions of each of these blocks are:

RACKET: Simple counter which increases/decreases the racket value (leftracket/rightracket) if the up/down (e.g. upleft/downleft) is asserted. For the Actel ProASICplus starter kit I have connected these up/down inputs to the microswitches. However, if you want to play the game properly you need to connect them to a gamepad or joystick.

BALLSPEED: This module creates the clock enable signal (clken) which drives the BALL_COOR finite statemachine. The speed of the ball is determined by this module. You can change the ball speed by setting the input signal speed(0) (pin 18) and speed(1)  (pin39) ("11"=slowest  "00" fastest). This module also creates an update pulse for the racket bar. You can control the racket speed by setting speed(2) (pin 124, 1=slow, 0=fast). Next to each of these pins is a VDD and GND signal so you can use a 2-pin jumper to tie them high or low.

PLL: The PLL creates the 25.176MHz video clock. The input clock on the ProASICplus starterkit is 40MHz which is first up-converted and then divided to create the video clock. I used ACTGEN macro builder to create this module (pll.vhd). This is the only module which is FPGA technology specific.

BALL_COOR: The ball position is determined by this finite statemachine. The screen, ball and racket dimensions are defined in the pingpong_pkg1.vhd package file.

MVGA: Mono-VGA controller (mvga_rtl.vhd). This module generates the HSYNC(31.77us), VSYNC(59.94Hz) and green only video output signal. This module requires no memory since it simply compares the HSYNC and VSYNC positions with the ball, racket and score position and turns the video on ('1') when they are equal. Thus the video memory is replaced by a rather large comparator function. This can easily be done if the number of screen objects is low but probably result in too much hardware for a "space-invaders" type of game. To drive the VGA signals you need to use a 270ohm series resistor if you use 3.3v drive signals. The maximum level is 0.7volt for green and 0volt for black, the VGA input impedance is 25ohm.

  

SCORE: As the name implies this module keeps track of the score. It reads the ball coordinates (ballx/bally) and when they either reach the left  (xpos=0) or right wall (xpos=MAX) increases the opposite score (left wall increases the right score and vice versa).

Gamepad

The ProASICplus Starterkit used microswitches can not be used to play the game (only good for testing). You can however quite easily replace the switches with some proper gamepads. You can buy gamepads for hardly any money. I bought mine from Curry's in the UK for £4.99 each. The modifications are easy, you need to cut the tracks around the up and down keys and re-connect to the wire as shown in the figure below. I would suggest you connect both up and down switches in parallel to accommodate left and right handed players. Pin55 and 63 are used for the left down and up key respectively and the same for pin69 and 79 for the right side.