RCORE54 PROCESSOR

Small 33 instruction RISC processor with a build-in UART

Last Updated: 19-Nov-2003

 

Introduction

This page describes a small microprocessor design called “Rcore54” implemented using Mentor Graphics HDL_Designer, Modelsim PE/SE and Leonardo Spectrum. The core is binary compatible with Microchip’s PIC16C52/54 microcontroller, however, I can not guarantee that the core is fully functional and/or suitable for any application (the usual legal stuff :-).

The core is developed under the terms of the GNU Lesser General Public License as published by the Free Software Foundation; either version 2.1 of the License, or  (at your option) any later version. The full text can be found at: http://www.gnu.org/copyleft/lesser.txt

Tools and versions I used to develop Rcore54 are:  Simulation Modelsim PE/SE 5.6d                     

I don’t have HDL Designer!

If you don’t have access to HDL Designer you can browse the design by clicking here (requires Javascript). The source files can be found in the hdl directory, a standalone basic Spectrum synthesis script synth.tcl and Modelsim script run.tcl can be found in the work_ls and work_mti directory respectively.

Rcore54 Design

The Rcore54 processor is a simple 33 instruction RISC core instantiated together with a single channel UART. The core is binary compatible with Microchips PIC16C52/54 controller. A large number of VHDL and Verilog implementation of this processor can be freely downloaded from the web. Excellent example are Massimo’s Conti PIC Core (documentation is in Italian), Opencores PPX16, or Tom Coonan’s VHDL and Verilog versions to name a few.  A commercial fully qualified version is available from Cast.

The reason why this processor is so popular are the excellent free development tools available from Microchip and others, the relative simplicity of the processor architecture, the powerful instruction set and the many hobbyist development boards. There are also a number of C-Compilers available for this processor. For this design I use BKD’s CC5x compiler which is also freely available from their website. It must be noted that this free edition model has some optimisation and code size restriction.

Setting up HDL Designer

1)  Invoke HDL_Designer and select Options->Library Mappings->Add, Add Rcore54 as the library name and browse to the directory above the Rcore54 directory. Next select the advanced button and add the subdirectories for Modelsim (<user_dir>\Rcore54\work_mti), Spectrum (<user_dir>\Rcore54\work_ls) and the Generic 1 File subdirectory (<user_dir>\Rcore54\Generic). Click OK and Save. After opening the library you should see all the design units.

Figure 1

For those who are unfamiliar with HDL designer, the src directory contains all the design entries be it HDL text or graphics, the hdl directory contains all the generated HDL files from graphics and text. The work_mti and work_ls are the working directory for the Modelsim simulator and Spectrum Synthesis tool respectively. The repository directory contains the RCS revision control repository files and directories and finally the generic and CCS5 directory contains foreign executables used in this project.

2) Download the CC5X C-compiler from here and save it in the CC5x subdirectory. Unzip the file (cc5xfree.zip, 358KB).

3) Download the PIC development tools MPLAB IDE v5.xx (Assembler, linker, simulator) from here. The file is nearly 14MB. Unzip and install the tools. You need to manually add the MPLAB directory to the search path variable!

4) The MPLAB assembler and CC5X C-Compiler are added as foreign tools to HDL designer such that they can be invoked with a single mouse click. To add the tools select the Tools->Customize tab->New Tool and add the settings as per figure 2. Note that both tools are invoked from DOS batch files, these files are located in the testbench (Rcore54_tb) User Data directory. The icons for the assembler and C-compiler can be found in the bitmaps directory.

Click to show large image

 

Click to show large image

Figure 2

5) To enable the custom tools you need to restart HDL Designer. After the restart select one of the C-files in the Testbench User Data and click on the CC5x tool button. The log window should show the output of the compiled file in hex.

The same applied to the Assembler file. If either of the tools is not working check the DOS search path.
 

Implementation

The Rcore54 design will be described top-down starting from the testbench. For more information regarding the capability of the core the user is referred to the PIC16C52/54 datasheets.
Figure 3 shows the testbench for the Rcore54 processor. The testbench is relative simply and consist of a number of clock generators (CLKGEN), an instantiated ROM core (Rcore_prom) and 2 monitors (TX_Mon and BUS_Mon) to monitor the processor output.

Figure 3 TestBench

The Clock generators can be configured using the generics, simply double click on the generic and change the period value.

The ROM core reads a hex file into a memory array during the simulation elaboration stage. The input file for this ROM is located in the testbench side data (User Data subdirectory). The filename is fixed to testf.hex. When the user assembles or compiles a file the output is written to this file. This allows different programs to be loaded into the processor without re-compiling the code.

Depending on the debugging mode the user can either write disassembled code to the transcript window (EN_TRACE=1), to a textfile text file (EN_TRACE=2) or disable the output all together (EN_TRACE=0).

The 2 monitors can be used to show the executed instruction in either the Modelsim transcript window or the write the results to a text file (simdump.txt located in the work_mti directory).

The TX_Mon monitors the UART transmit pin and copies any ASCII string received to the Modelsim Transcript window. The monitor displays the string when an ASCII CR character has been received or after 40 characters which ever comes first. The UART is connected in loopback mode which means that any transmitted characters are echoed back to the receive unit.
 

Figure 4 EN_TRACE generic

The Time_out bit TO and Power_Down bit PD are connected to 2 VHDL assert statements using a “yellow block”. Yellow blocks allow bits of code to be grouped under a symbol; the code is written to the architectural section of the generated code.

Figure 5 shows the Rcore54 processor and the single channel UART. The UART Transmit and Receive hold register are mapped to register address 0x07. This address is a general purpose register in the 16C52/54. The core can easily be changed to a 16C55, which contains 3 Parallel I/O port, for this, the UART register needs to be remapped to a different address, the rxhold_c and txhold_c generics can be used for this purpose.

Figure 5 Rcore54 Top Level

The UART transmit and receive clock are derived by a fix divider from the processor clock (14.7456MHz). The divider value is a generic called txdiv16_I and can be calculated using the following formula:

txdiv16_I=(system_clock/[16*baudrate])-1

The processor core is shown in figure 6, this is the last graphics level, all block shown are implemented in VHDL. Figure 6 clearly shows how each individual blocks are connected, this must be easier to understand than 7 component instantiations!

Figure 6 Processor Core

Simulation

Simulation is strait forward, select the testbench and click on the Modelsim Icon. A dialogue box will pop up (3) which allow you to set some simulation parameters.

Figure 7 Simulation of Rcore54

 
Enter “tb.do” in the Initialisation command box (see Note). This will result in the “tb.do” script being executed after the design has been loaded. The file is located in the Modelsim Downstream directory.

The testbench contains two assert statements, one “severity failure” is connected to the power_down bit and one “severity note” connected to the timer time_out bit. The power_down assert is used to stop the simulation, see software development section.

Synthesis

As with simulation, the core can be synthesised and place and routed with only 3 mouse clicks. Select the Rcore54 design (DUT) and click on the Spectrum, Precision or 3rd party synthesis button.

Figure 8 Synthesis of Rcore54

Gate level simulation

To import the gatelevel netlist, right click on the Rcore54 and select the Rcore54 netlist and sdf file. As depicted in fugure 9 the blue array (default view) now points at the imported netlist. To revert back to the rtl simulation simply change the default view (right click on Rcore54) and select the synthesis.bd file.

Figure 9 gatelevel simulation

To perform gatelevel simulation set the default view to the Rcore54_out netlist, highlight the testbench and click on the Modelsim button. HDL_Designer will now pass on the gatelevel netlist to Modelsim. The Rcore54 testbench uses signal spy to interrogate internal signals and registers. This cannot be used on the gatelevel design (unless signal names are preserved during synthesis). Before doing the simulation disable the disassembler by setting the EN_TRACE generic on the testbench sheet to 0 (see figure 3). Also make sure the modelsim.ini file contains the correct primitive library mappings.

Software development

To assemble/compile one of the testfiles, select one of the sources files located in the testbench side datawindow and click on the MPASM or CC5x buttons as shown in figure 10.

After the file has been assembled/compiled the string length of each line within the hex file is adjusted to a fixed number of characters. This has been done to make reading of the file easier in VHDL. The utility to perform this action is located in the generic subdirectory (FIXLEN.EXE). In order to keep the number of files down in the user directory the generated intermediate files are deleted.

The DELEXT.EXE utility (also located in the generic directory) takes as an argument the basename+extension and deletes files with extensions specified as its argument.

Figure 10 Assembler/Compiler invocation

For example:                DELEXT basename.asm .hex .lst .occ

Will delete the file basename.hex, basename.lst and basename.occ This utility was developed since there is no way in the current HDL_designer 2002.1b version to specify the basename as an argument.

Supplied Testprograms

Only a few test programs are provided located in the testbench User Data Directory. These test programs do not fully test the processor; this is left as an exercise to the reader :-).

TSTRCORE.ASM

This assembly program executes all 33 instructions and output the result to PORTA and PORTB. Using the parallel output port for test results will also mean the test can be carried out for gatelevel simulation. The comments in the source file shows the expected result.

FLOAT.ASM

Float.asm is one of the examples programs from application note AN554. The program has been slightly modified to echo the results onto PORTA.

TSTWD.ASM

Simple program to test the watchdog timer. Make sure the watchdog is enable, see Rcore_pkg packag

--***************************************************************************
-- Watchdog
-- Watchdog timer wdmax_c should be set to 55Hz=XTAL/dmax_c
-- (e.g 32.768KHz watch xtal divided by 589)
--***************************************************************************
  constant wdte_c            : std_logic := '0';      -- 1=enable watchdog, 0=disable
  constant wdmax_c           : std_logic_vector (9 downto 0)  :="0000100111";

TSTTIMER.C

TSTTIMER test the general purpose timer, the program also shows how Rcore54 registers can be modified using the CCx5 C-Compiler.

TSTSTR.C

This programs sends a string to the UART. The testbench redirect the transmitter output to the receiver input (loopback) thus testing the transmitter and the receiver. The testbench also contains a UART monitor which echo’s any valid string received to the Modelsim transcript window.

RCORE54.INC contains some predefined directives.

Have fun.