VH2SC

VHDL to SystemC Converter

web:www.ht-lab.com
Last Updated: 20/07/08

 

VH2SC is a free basic VHDL to SystemC converter. The converter handles a small subset of Synthesisable VHDL 87/93 language constructs. The current version translates all VHDL IEEE types to sc_int/sc_uint/integers and booleans this in order to maximise performance. The aim of the converter is to produce a cycle accurate model of synthesisable VHDL code. The converter runs on Windows.

Some wording of advice, don't try to convert the Leon core with it, it is simply too complex to handle. VH2SC is not a compiler, it is a language construct translator and as such the VHDL constructs it can handle are rather limited. If you are serious about translating your VHDL to SystemC and need the fastest available converter with all the guarantees of cycle accuracy etc, than I can highly recommended the VSP compiler from Carbon Design Systems in the US. I used this product for a while and I can tell you this is some impressive piece of technology!

Let me know if this utility is helpful in anyway. If you want anything changed or added just send me an email. If I have the time and the update is not that difficult I might add it :-)   This utility is no longer maintained. This is mainly due to the parser which is hacked so much that fixing one bug will result in 10 new ones.

  1. License Agreement
  2. Download Software
  3. Installation
  4. Example Usage
  5. Performance
  6. Limitations
  7. VH2SC Command-line options
  8. FAQ
  9. Links

1. License Agreement

The VH2SC converter is licensed under the Aladdin Free Public license (AFPL). This means it can be freely used for non-commercial purposes.  

2. Download software

Make sure your run a virus checker on the executable files before executing them!

3. Installation

Unzip the file to a suitable directory. Look in the example directory for some working models.

4. Example Usage

Before you run vh2sc on your VHDL code make sure that:

a) You have read the Limitations section
b) Your code has 1 entity+architecture/package per file.
c) Your code is error free and synthesisable.
d) You have a testbench to verify the generated SystemC code.

4.1 Example1: Simple counter

    c:\VHDL2SystemC\example1>vh2sc -v -mti count.vhd

    VH2SC -> VHDL to SystemC Converter
    Ver 0.21 ** Alpha Release **  (c)HT-Lab 2007
     
    SQLite Version         : 3.3.13
    Parsing File           : count.vhd
     
      Line 9    ** Info    : library ieee ignored
      Line 28   ** Info    : VH2SC Translation Disabled
      Line 32   ** Info    : VH2SC Translation Re-Enabled
      Line 37   ** Info    : process() translated to process_line37
     
    Writing Header File    : cnt.h
    Writing C++ File       : cnt.cpp
                ** Info    : Modelsim SC_MODULE_EXPORT(cnt) macro added

    c:\example1>AStyle --style=kr -n cnt.cpp cnt.h

    Artistic Style 1.20.2
    formatting cnt.cpp
    formatting cnt.h
    total time 0.015 seconds

4.1.1 Simulation using Modelsim

If you have access to Modelsim (PE/SE+SystemC option) than the simulation/validation step is simple, just compile the cnt.cpp module instead of the count.vhd file. I would advice to clean the work library (vdel -all; vdel -allsystemc, or rm -Rf work, or del /Q/S work) before compiling the code (it seems that the _opt file from a previous VHDL simulation can result in an error during elaboration).

Visually comparing the waveforms from a VHDL and SystemC simulation is obvious not the way to confirm that the generated model is cycle accurate. Modelsim SE supports a very handy waveform compare option which is one of the methods I use in my regression test. A better method is to write a self checking testbench that confirms the result after simulation. Calypto makes equivalent checkers for RTL and SystemC, this is obvious the best solution but you might need a serious EDA budget for that :-).

Note: the fatal SystemC error is generated by the SC_REPORT_FATAL macro and is used to stop the simulation. This is just an example to show how vh2sc translates assert statements and should not be consider good coding practice.

4.2 Example2: AES Core

The second example is the modified 128bits AES86 core which you can find here. This design has a self checking testbench so is easy to validate. To convert the design to SystemC use the following sequence:

4.3 Example3: Simple Cordic Core

The third example shows how vh2sc handles packages and sliced signals. When a package is converter vh2sc will automatically write an SQLite(tm) database file. This file is then read whenever the package is referenced.

When you execute the run.bat file you will see the following Info line :

This informs the user that an extra variable has been added to the generated source. This variable is required if the VHDL contains sliced assignments, for example:

xreg_s is translated into sc_signal, unfortunately there is no part select method for sc_signals so in order to support constructs like this the signal is read into a variable at the beginning of the process, modified as per the VHDL and then written back to the signal at the end of the process,

5. Performance

The simulation speed of the generated code is generally much slower than the equivalent VHDL. This might come as a surprise and disappointment to some. SystemC can run much faster than VHDL/Verilog but only when used at a higher level of abstraction. The generated SystemC code is at the RTL level which means that communication between the modules is at the so called pin level. This type of communication is very demanding in terms of events and this is what is slowing down the performance. In most cases when you write a SystemC model you are not interested in the way that subblocks communicate. For example, using a function call (transactor) to write data into a memory block is much faster than simulating all the signals that are associated with say a DDR3 hardware model.

In addition to the above vh2sc generates inefficient code. To start with, all the combinatorial logic is written to the same process. This means that if you have large amount of combinatorial logic a high-frequency signal will trigger and execute all that combinatorial logic even when this is not required for most of it. This is not the way that VHDL/Verilog simulation operates. In this case only the logic associated with the high-frequency signal is schedules and executed.

The second problem is that the translated code follows the VHDL coding style, for example a rising_edge(clk) process is translated as:

VHDL

SystemC

process (clk)
     begin
         if (rising_edge(clk)) then

    void process_linex() {
               if (clk.posedge())

    SC_METHOD(process_linex);
    sensitive << clk;

The above code will result in the process_linex to be triggered on both edges of the clock. A better solution is to change the sensitivity list such that the process is only triggered on the rising edge of the clk (sensitive << clk.pos();).

6. Limitations

The following constructs are not (yet?) supported :

7. VH2SC Command-Line options

NAME

SYNOPSIS

DESCRIPTION

OPTIONS

-q quiet mode, suppress all warnigs and info messages
-v verbose mode, show all info messages
filename VHDL input filename
-c2h Write all generated code to header file
-oh <filename> Specify output header filename (default:entity_name.h)
-oc <filename> Specify output cpp filename (default: entity_name.cpp)
-ip Ignore synthesis/translate/vh2sc pragmas
-mti Add SC_MODULE_EXPORT(modulename) to cpp file
-ncsim Add NCSC_MODULE_EXPORT(modulename) to cpp file
-sql Force an SQLite datebase file

8. FAQ

For any other questions or comments please use the feedback form

9. Useful Links