ProASIC+ Prototype Board

Some time ago I got hold of a ProASIC+ development board. This board was designed by Luca Cattaneo, one of Actel's TME. On the web you can find a number of home-brewed FPGA boards mostly based on Xilinx FPGA's. To give some balance to this situation I have asked Luca if I could add his board design schematics to my website.

Why would you consider building your own ProASIC board? Well the main reason might be that Actel is one of the few companies who uses the PQ208/PQ240 package for its biggest device (A3PE3000PQ208) and this package can still be hand soldered. Another reason might be that as far as I know there aren't any low cost ProASIC boards currently on the market, so using an APA1000PQ208/A3PE3000PQ208 for a custom build board might not be such a bad choice.

You can download the documentation which includes PCB layout shots from the link below. I would recommend that you add a heatsink to IC10 and IC8 (see picture above) since they can become quite hot. The original board came with an APA450 which I changed to an APA1000.

• Download ProASIC+ prototype board schematics (1.2MByte zipped)
   

Example: Porting the CPU86 Processor Design

I have ported the 8088 CPU86 FPGA processor design to Luca's board, the design can be downloaded from the link below. As a minimum you need an APA600 but an APA450 might also work provided Actel's Designer can handle an FPGA that is 98% full (I haven't tested this yet).

• Download CPU86 Design for the ProASIC+ family (428KByte, zipped)

Also included in the zip file is a debug monitor called MON88.

Click to enlarge

The complete design consist of the CPU86 processor, an Intel Hex bootloader (256Bytes LUT), 2 UART's, a RealTime clock and a parallel I/O port. All three peripherals are located in the superio_top block. The superio name is a bit of a misnomer since the peripherals are far from super, in fact they are extremely basic. However the point was to get something up and running with the least amount of complexity, if you want you can always add some opencores peripherals :-). The superio_bock has 3 VHDL generics:

COM_DIVIDER   = 15        ( integer )  
TMR_DIVIDER91 = 107927    ( integer )  
UART2_G       = TRUE      ( boolean )  

These generics set the baudrate clock for the UARTs, the timer and enables the second UART (if UART2_G is set to TRUE). I use one of the ProASIC+ PLL clocks to create a 9.8214MHz (9.8304MHz requested) from the 50MHz oscillator clock. I have chosen this values since it is divisible by the required baudrate clock of 16*38400 and it enables the RTC timer unit to create a reasonable accurate 91Hz clock signal. The COM_DIVIDER value is calculated as follows:

COM_DIVIDER= { CLK/(16*BAUDRATE) }-1

The Real Time Clock (RTC) use the 91Hz clock to create a 1 second pulse for keeping the time and 18.2Hz pulse for other BIOS timing functions.  Note that the 18.2Hz signal is not yet used. The RTC provides the time, date and takes care of leap years. The MON88 debugger/monitor use the RTC hour/minute/second values to work out the BIOS "number of ticks since midnight" value. The TMR_DIVIDER91 is calculated as follows:

TMR_DIVIDER91 = CLK/91

The top 256 bytes of the 8086 1Mbyte memory map is taken up by the Intel Hex bootstrap loader, the boards 64Kbyte of SRAM is located in the first 64Kbyte. The 128Kbyte FLASH memory has been mapped to address 256KB to 378KB, note that I have not yet tested the FLASH interface.

Use the following sequence to get the processor up and running.

1) Download the CPU86 EDIF file and unzip to a suitable directory (keep the directory structure)

2) Navigate to the Precision directory

The zip file includes a simple synthesis script for Precision Synthesis (see \precision\run.tcl). Execute the run_precision.bat file in a DOS box or from a Cygwin shell. For any other synthesis tool use the filelist order as shown below (see run.tcl file).

../rtl/clockgen.vhd
../rtl/pio_rtl.vhd
../rtl/timer_fsm_fsm.vhd
../rtl/timer_top_struct.vhd
../rtl/uarttx.vhd
../rtl/uartrx.vhd
../rtl/uart_struct.vhd
../rtl/superio_top_struct.vhd
../rtl/Bootstrap_rtl.vhd
../rtl/cpu86.vhd
../rtl/top_struct.vhd

3) Navigate to the place_route Directory

For place and route I have used Designer 6.2+SP1. In the place_route directory you can find a simple Designer script called run.tcl. You can either call this script from within Designer or run Designer in command line mode by executing the run_pr.bat file. The script expects the top.edf file to be located in the ../precision/cpu86_actel_impl_1/ directory, modify the script if this is not the case.

import_source -format "edif" -edif_flavor "MGC" \
 {../precision/cpu86_actel_impl_1/top.edf} -format "gcf" \
 {./actel_board.gcf} -merge_physical "no" -merge_timing "yes"

The board pin out is specified in the actel_board.gcf file which you find in the place_route directory.

The script takes about 2 hours to run on a AMD3500+. The CPU86 + basic peripherals takes about 24% of the APA1000.

Part-Package: APA1000-PQ208
        Core Slots:        56320
        RAM/FIFO Slots:       88
        I/O Slots:           158    (Globals: 4)   (PLLs: 2)
Core Cells:      13139  -->  Usage: 23.3 percent
RAM/FIFO Cells:      0  -->  Usage: 0.0  percent
IOs:                69  -->  Usage: 44.2 percent
PLLs:                1  -->  Usage: 50.0 percent

The reported maximum clock frequency is only 15.4 MHz. There are 2 reasons for this, the first one is that the edif file has been optimised for area and not for delay, the second and main reason is that the decoding process contains a number of look-up tables. Since the ProASIC+ does not have any ROM modules the look-up tables are synthesised to logic which significantly reduces the Fmax. 

Clock Domain:               CLKGEN_Core:GLB
Period (ns):                64.888
Frequency (MHz):            15.411

3) Download the design

After place and routing the design download the cpu86.stp STAPL file into the device. Using a Flash-Pro Lite on a parallel port takes about 20 minutes.

4) Upload the MON88 Monitor

Next, connect the serial port and start up a terminal program like Teraterm. The UART defaults to 38400,N,8,1. When you press reset (SW1 on the prototype board) or powerup the board you will see nothing more than a '>' character appearing on the screen. This is an indication that the Intel Hexloader is ready to accept an upload (see bootloader\ldintel.asm for the source). Next upload the MON88 debugger/monitor, see the MON88 link for more info on how to do this.

5) Try some test program

When the MON88 monitor has been uploaded press '?' to get a help screen. To upload a program to the monitor you need to assemble the source followed by converting it into an Intel Hex file. See again the MON88 link on how to do this. If you use the standard BIOS calls for reading and writing to the screen you can try out your program first using debug.exe before uploading it to the prototype board. If you find any difference please let me know!