Modelsim SE UART-Socket FLI Demo

Last Updated: 14-Sep-2003

 

 

This page contains a simple example of a UART connected via the FLI interface to an external terminal. Characters transmitted to and received from the terminal will be re-directed to the UART.  For this demo the UART is connected in loopback mode (TX connected to RX) so that any characters typed in on the terminal will be echoed back.

The socket interface code is very generic and can easily be adopted for other TCL communication purposes like connecting Matlab to Modelsim or connecting 2 Modelsim simulators.

Download Demo Files

Windows/Linux version (zipped, 90 KB)
 

Software used

• Modelsim 5.7e SE,  note the PE version can not be used for this demo due to the FLI interface.
• HDL_Designer 2003b, this is optional, you can run the demo using Modelsim only
• Microsoft Visual C/C++ 6.0, optional if you want to modify/re-compile the FLI C-source file under windows.
  Note: for some reason my Cygwin (1.3.22)  failed on this demo. If you compile the source (GCC 3.2) and run up the demo you will receive spurious characters. I am not sure what is causing this but I suspect a "feature" in the Cygwin Socket layer. The Linux version works fine.
  
• GCC 3.2.2 Redhat 9, optional if you want to modify/re-compile the FLI C-source file under Linux
• Any Terminal Software, for example :
• Java based terminal, Invoke from a DOS box/Cygwin/Linux shell with java -jar jta20.jar <computer_name> <port_number>
• Use the Linux/Cygwin build-in Telnet Client, invoke with telnet <computer_name> <port_number>. Note: you will only see the characters being echoed back after pressing return.
• Use a more fancy terminal, for example (windows only) Eric's Telnet98
   

Running the Demo

• Make sure you can ping the computer running the terminal software.
• Invoke Modelsim, browse to the UART_FLI directory.
• Create a working library:  vlib work
• Create a library mapping from uart_fli to work:  vmap uart_fli work
• Compile source files located in the hdl directory:
• vcom -work uart_fli -just p hdl/*.vhd
• vcom -work uart_fli -just b hdl/*.vhd
• vcom -work uart_fli -just e hdl/*.vhd
• vcom -work uart_fli -just a hdl/*.vhd
• Compile the socket FLI C-source, change to the fli/fli_linux directory and execute compile (.bat)
• Check that the file uart_test.so is copied to the current directory (UART_FLI).
• Start the simulator (elaborate): vsim uart_fli.uart_fli_top_tb
• Enter the computer name and port number running the terminal software.
• If all is OK Modelsim will respond with "Opening socket <number> on <name>, Waiting for connection"
• Next start your terminal software (e.g. using Cygwin : telnet <computer_name> <port>)
• Modelsim will continue the load and report : "Load Done: Adding socket callback"
• Next execute run -all
• Start typing something on the terminal window, you should see the same characters typed in being echoed back.

Note: HDL_Designer users, compile the FLI C course as described above but copy the uart_test.so to Modelsim's work directory instead.
Note: you may want to use the -wlfslim vsim argument if you are running long simulation (see Modelsim's Command Reference manual).
 

FLI Code

To look at the source code in HTML click here. If you compile the code for Windows use #define WIN32 otherwise comment it out. You might also want to comment out the #define ASK_SERVER_NAME line and fill in your server name and port number as shown in the example below.

//#define ASK_SERVER_NAME

#ifndef ASK_SERVER_NAME
    #define PORTNUMBER  2000
    #define SERVERNAME  "achilles"
#endif

The receiver (Terminal to UART) contains a simple FIFO. You can set the FIFO depth using the #define MAXBUFFER variable.