LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY fsmb IS
   PORT( 
      a     : IN     std_logic;
      b     : IN     std_logic;
      clk   : IN     std_logic;
      reset : IN     std_logic;
      x     : OUT    std_logic;
      y     : OUT    std_logic
   );
END fsmb ;

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ARCHITECTURE fsm OF fsmb IS

   -- Architecture Declarations
   TYPE STATE_TYPE IS (
      s0,
      s1,
      s2,
      s3,
      s4
   );

   -- State vector declaration
   ATTRIBUTE state_vector : string;
   ATTRIBUTE state_vector OF fsm : ARCHITECTURE IS "current_state" ;


   -- Declare current and next state signals
   SIGNAL current_state : STATE_TYPE ;
   SIGNAL next_state : STATE_TYPE ;

   -- Declare any pre-registered internal signals
   SIGNAL x_int : std_logic  ;
   SIGNAL y_int : std_logic  ;

BEGIN

   ----------------------------------------------------------------------------
   clocked : PROCESS(clk,reset)
   ----------------------------------------------------------------------------
   BEGIN
      IF (reset = '0') THEN
         current_state <= s0;
         -- Reset Values
         x <= '0';
         y <= '0';
      ELSIF (clk'EVENT AND clk = '1') THEN
         current_state <= next_state;
         -- Registered output assignments
         x <= x_int;
         y <= y_int;

         -- Default Assignment To Internals

      END IF;

   END PROCESS clocked;

   ----------------------------------------------------------------------------
   nextstate : PROCESS (a, b, current_state)
   ----------------------------------------------------------------------------
   BEGIN
      -- Default Assignment
      x_int <= '0';
      y_int <= '0';
      -- Default Assignment To Internals

      -- Combined Actions
      CASE current_state IS
      WHEN s0 =>
         IF (a = '1') THEN
            next_state <= s1;
         ELSIF (b = '1') THEN
            next_state <= s3;
         ELSE
            next_state <= s0;
         END IF;
      WHEN s1 =>

         x_int <= '1' ;
         IF (a = '0') THEN
            next_state <= s2;
         ELSIF (a = '1') THEN
            next_state <= s4;
         ELSE
            next_state <= s1;
         END IF;
      WHEN s2 =>

         x_int <= '0' ;
         y_int <= '1' ;
         IF (a='0') THEN
            next_state <= s0;
         ELSE
            next_state <= s2;
         END IF;
      WHEN s3 =>

         x_int <= '1' ;
         IF (b = '0') THEN
            next_state <= s2;
         ELSE
            next_state <= s3;
         END IF;
      WHEN s4 =>

         x_int <= '1' ;
         IF (a = '0') THEN
            next_state <= s2;
         ELSE
            next_state <= s4;
         END IF;
      WHEN OTHERS =>
         next_state <= s0;
      END CASE;

   END PROCESS nextstate;

END fsm;