Papers Page

 

• System-On-Chip Data Processing and Data Handling Spaceflight Electronics (PDF, 433KB)

Kleyner I, Tiggeler H.A.B, Katz R, Reconfigurable, System-On-a-Chip, High-Speed Data Processing and Data Handling Electronics, Proceedings MAPLD 99 Military and Aerospace Applications of Programmable Devices and Technologies, Maryland USA 1999.

Abstract 
This paper presents a methodology and a tool set which implements automated  generation of moderate-size blocks of customized intellectual property (IP), thus effectively reusing prior work and minimizing the labor intensive, error-prone parts of the design process. Customization of components allows for optimization for smaller area and lower power consumption, which is an important factor given the limitations of resources available in radiation-hardened devices. The effects of variations in HDL coding style on the efficiency of synthesized code for various commercial synthesis tools are also discussed.

• Experiences Designing a System-on-a-Chip for Small Satellite Data Processing and Control (ZIP, 1.38MB)

H.Tiggeler, T.Vladimirova, D.Zheng, J.Gaisler. Experiences Designing a System-on-a-chip for Small Satellite Data Processing and Control - Proceedings of International Conference on Military and Aerospace Applications of Programmable Devices and Technologies (MAPLD'2000), P-20, September 2000, Laurel, Maryland, US, NASA.

Abstract
The continuous evolution of communication satellite platforms demands the use of modern approaches to system design. A system-on-a-chip realising the main functions of an on-board computer is an important step towards further minituarisation of small satellites. This paper describes a single-chip implementation of a simplified version of a Surrey Satellite Technology Limited (SSTL) on-board computer. The specification of the system and a prototype based on a XILINX Virtex FPGA are discussed. Synthesis results of the microprocessor and peripheral IP cores are reported.

• A (16,8) Error Correcting Code (t=2) for Critical Memory Applications (PDF, 103KB)

Hodgart M.S. and Tiggeler H.A.B, A (16,8) Error Correcting Code (t=2) for Critical Memory Applications, Proceedings DASIA 2000 Data Systems In Aerospace, 2000.

Abstract
High density SRAMs generate errors in their stored data because of natural radiation. This is a particular problem for computing on-board a satellite , where the single-error correction of the usual Hamming code can be inadequate. The two-bit error correcting code described here is a more powerful and efficient alternative.

Sandi Habinc from the European Space agency produced a generic VHDL version of the code which can be downloaded here (ZIP, 17KB).
Also read Rich Katz application note on the subject

• Fast Low Complexity Reed Solomon Codec for Space and Avionics Ramdisk Applications (PDF, 352KB)

Hodgart M.S. and Tiggeler H.A.B, Fast Low Complexity Reed Solomon Codec for Space and Avionics Ramdisk Applications, Proceedings DASIA 98 Data Systems In Aerospace, 1998.

Abstract 
We describe an application of the RS code to the routine error protection of large RAM memory for satellites in low Earth orbit. Errors are normal in this environment - an estimated 1000 soft errors per day for 128 Mbytes of memory being typical. There is a need to free up the CPU from most or all of the required encoding and decoding, and use a dedicated codec. The device is mostly transparent to the routine transfer of data between CPU and RAM disc Our choice of codec uses FPGA technology. The application requires correction of a maximum of two (byte) errors per block of 512 bytes of data. This limited number of corrections obviates the need for standard decoding methods. A form of direct decoding is adopted that allows very considerable simplification of the codec with a low internal clock rate and low physical complexity

•  FPGA Implementation of Sine and Cosine Generators Using the CORDIC Algorithm (PDF, 345KB)

T.Vladimirova, H.Tiggeler. FPGA Implementation of Sine and Cosine Generators Using the CORDIC algorithm, in Proceedings of Military and Aerospace Applications of Programmable Devices and Technologies International Conference (MAPLD'99), A-2, 28-30 September 1999, Laurel, Maryland, US, NASA publ.

Abstract
The aim of this paper is to investigate CORDIC schemes for fast and silicon area efficient computation of the sine and cosine functions that are suitable for FPGA-based implementation. The results of theoretical investigation into redundant CORDIC is presented. Summary of CORDIC synthesis results based on Actel and XILINX FPGAs is given. Finally applications of CORDIC sine and cosine generators in small satellites are discussed.

A simple serial Cordic implemented in VHDL can be downloaded from here

•  A CCSDS Software System for a Single-Chip On-Board Computer of a Small Satellite (PDF, 241KB)

I.Rutter, T.Vladimirova, H.Tiggeler. A CCSDS Software System for a Single-Chip On-Board Computer of a Small Satellite - 15th AIAA/Utah Sate University Conference on Small Satellites, Utah, USA, August 13-16 2001, SSC01-VI-4.

Abstract
The work presented in this paper is part of a Surrey Space Centre research project that aims to reduce the size of an on-board computer to a single chip facilitating further miniaturisation of small satellites. The paper is concerned with a communication system, specifically designed to meet the needs of a single-chip onboard computer - a simplified yet reliable and automated standalone alternative software implementation of the Consultative Committee of Space Data Systems (CCSDS) protocol communicating with a standard universal asynchronous receiver-transmitter (UART) peripheral. Details of the design and implementation stages of a CCSDS package coded in the language C are given. A thin hardware layer is described which translates the asynchronous UART stream into a CCSDS compliant synchronous stream. Synthesis results targeted at Actel FPGAs are presented taking into account single event upset tolerant coding styles.

• Reconfigurable Single-chip On-Board Computer for a Small Satellite (PDF, 151KB)

D.Zheng, T.Vladimirova, H.Tiggeler. Prof. Martin Sweeting. Reconfigurable Single-Chip On-Board Computer for a Small Satellite - 52nd International Astronautical Congress, Toulouse, France - October 1-5, 2001, IAF-01-U3.09

Abstract
Small Satellite electronic components are generally unavailable for physical upgrade or repair after launch. Run-time Reconfigurable (RTR) computing technology of SRAM-based Field Programmable Gate Arrays (FPGAs) allows to overcome this problem - application of RTR can facilitate new hardware circuits to be uploaded via a radio link without an interruption of service in the FPGAs. In this project these advances in microelectronics are used to produce a key enabling technology for a new generation of low-cost commercial, scientific and military small satellites. This paper introduces a reconfigurable single-chip on-board computer (RSC-OBC) and      proposes two schemes for its on-board reconfiguration. Design issues related to reliable operation of the RSC-OBC in space are addressed.

• Designing a System-on-a-chip for Small Satellite Data Processing and Control

H.Tiggeler, T.Vladimirova, J.Gaisler. Designing a System-on-a-chip for Small Satellite Data Processing and Control, IIE Magazine on Engineering Technology, vol. 4, N 6, June 2001, pp. 38-42 (Engineering Technology, The Magazine of the Institution of Incorporated Engineers, ISSN 1462-2165)

Only available in printed form from the IIE

• Experiences with a COTS Real Time Operating System for a Satellite On Board Computer

Dachs A and Tiggeler H.A.B, Experiences with a COTS Real Time Operating System for a Satellite On Board Computer, Proceedings DASIA 99 Data Systems In Aerospace, 1999

Abstract
Surrey Space Centre (SSC) micro-, mini- and nanosatellites depend heavily on their on-board computers for performing tasks such as attitude control, payload support, communication and housekeeping. Recent improvements in the resolution of imaging systems and higher bandwidth communication links have resulted in further demands on the On Board Computers and software. This paper describes the experience gained and lessons learned from porting a popular Commercial Off The Shelf (COTS) operating systems to one of SSTLs on-board computers. The operating system described is QNX ® Real Time Operating system [1] developed by QNX Software Systems Ltd.